The present invention relates generally to semiconductors and more specifically to a trench fabrication process for making semiconductor memory devices.
Flash electrically erasable programmable read only memory (EEPROM) is a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a xe2x80x9cstacked gatexe2x80x9d structure or word line. The multi-layer stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate (poly1) overlying the tunnel oxide; an interpoly dielectric layer overlying the floating gate; and a polysilicon control gate (poly2) overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (deposited on the control gate), a poly cap layer (deposited on the gate silicide layer), and a silicon oxynitride layer (deposited on the poly cap layer) may be formed over the control gate.
In order to have the memory cell work properly, the stacked gate structure must have every layer properly aligned within nanometers of the previous layer. The worse the alignment, the worse the device performance will be. As the device shrinks, these nanometer shifts become a significant problem in that the memory cell will not operate.
A plurality of Flash EEPROM cells may be formed on a single substrate. A Flash EEPROM also includes peripheral portions, which typically include input/output circuitry for selectively addressing individual memory cells.
After the formation of the memory cells, electrical connections, commonly known as xe2x80x9ccontactsxe2x80x9d, must be made to connect the stack gated structure, the source region and the drain regions to other parts of the chip. The contact formation process includes the formation of sidewall spacers around the multi-layer stacked gate structures of each memory cell and a silicidation on the active region. An etch stop or liner layer, typically a nitride material such as silicon nitride, is then formed over the entire substrate, including the multi-layer stacked gate structure. A dielectric layer, generally of oxide such as borophosphosilicate glass (BPSG), is then deposited over the etch stop layer. A chemical-mechanical planarization (CMP) process is applied to the wafer and wafer-scale planarization is achieved. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings in the oxide layer. The contact openings stop at the source and drain regions in the substrate. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form conductive contacts. The substrate is then subjected to a CMP process, which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.
As can be seen from the above, precise placement and layering of the multi-layer stacked gate structure is imperative for future size reductions of memory devices.
A solution, which would allow further miniaturization of memory device without adversely affecting device performance has long been sought, but has eluded those skilled in the art. As the demand for higher performance devices and miniaturization continues at a rapid pace in the field of semiconductor, it is becoming more pressing that a solution be found.
The present invention provides a tunnel dielectric layer and a gate layer formed on a semiconductor wafer with a trench insulator of a shallow trench isolation (STI) used to form a floating gate structure which is self-aligned to the active region. The semiconductor device has improved floating gate properties and improved planarity when compared to conventional semiconductor devices.
The present invention further provides a method of manufacturing a self-aligned floating gate structure by forming a tunnel dielectric layer and a gate layer on a semiconductor wafer. A trench forming technique is used to form a shallow trenchl through the tunnel dielectric layer, the gate layer and into the semiconductor wafer. An insulator is deposited in the trench whereby the semiconductor device has improved floating gate properties and improved planarity when compared to conventional semiconductor devices.
The present invention further provides a method of manufacturing a floating gate structure which involves a reduction in the number of processing steps when compared to conventional fabrication techniques.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.